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An Approach for the Specification, Verification and Synthesis of Secure Systems

In this paper we describe an approach based on open system analysis for the specification, verification and synthesis of secure systems. In particular, by using our framework, we are able to model a system with a possible intruder and verify whether the whole system is secure, i.e. whether the system satisfies a given temporal logic formula that describes its secure behavior. If necessary, we are also able to automatically synthesize a process that, by controlling the behavior of the possible intruder, enforces the desired secure behavior of the whole system.

Electronic Notes Theoretical Computer Science, 2007

Autori: F. Martinelli, I. Matteucci
Autori IIT:

Tipo: Articoli su riviste non ISI con referee internazionali
Area di disciplina: Information Technology and Communication Systems
Da pagina 29 a pagina 43

Attività: Metodi formali per la sicurezza di sistemi ICT